1) Field of the Invention
The invention is in the field of Semiconductor Devices.
2) Description of Related Art
For the past several years, the performance of semiconductor devices, such as Metal Oxide Semiconductor Field-Effect Transistors (MOS-FETs), has been greatly enhanced by the incorporation of strained channel regions into the active portions of a semiconductor substrate, e.g. the use of compressively strained silicon channel regions to enhance hole mobility in P-type Metal Oxide Semiconductor Field-Effect Transistors (PMOS-FETs). The presence of such strained channel regions may greatly enhance the rate at which charge migrates in a channel when a semiconductor device is in an ON state.
FIGS. 1A-C illustrate cross-sectional views representing a typical process flow for forming strain-inducing source/drain regions in a PMOS-FET, in accordance with the prior art. Referring to FIG. 1A, a non-strained PMOS-FET 100 is first formed. Non-strained PMOS-FET 100 is comprised of a channel region 102. A gate dielectric layer 104 sits above channel region 102 and a gate electrode 106 sits above gate dielectric layer 104. Gate dielectric layer 104 and gate electrode 106 are isolated by gate isolation spacers 108. Tip extensions 110 and source/drain regions 112 are formed by implanting dopant atoms into substrate 114 and are formed, in part, to reduce the parasitic resistance of non-strained PMOS-FET 100. Thus, the source/drain regions 112 are initially formed from the same material as the channel region 102. Therefore, the lattice mismatch between the source/drain regions 112 and the channel region 102 is negligible, resulting in effectively no strain on the channel region 102.
Referring to FIG. 1B, portions of substrate 114, including source/drain regions 112, are removed by an etch process to form recessed regions 116 in substrate 114. Subsequently, strain-inducing source/drain regions 120 are formed by selectively growing an epitaxial film into recessed regions 116, as depicted in FIG. 1C. Strain-inducing source/drain regions 120 can be doped with charge-carrier atoms, e.g. boron in the case of a PMOS-FET, which may be carried out in situ or after epitaxial film growth, or both. In an example, substrate 114, and hence channel region 102, is comprised of crystalline silicon and the film grown to form strain-inducing source/drain regions 120 is comprised of epitaxial silicon/germanium. The lattice constant of the epitaxial silicon/germanium film is greater than that of crystalline silicon by a factor of ˜1% (for 70% Si, 30% Ge) and so strain-inducing source/drain regions 120 are comprised of a material with a larger lattice constant than that of channel region 102. Therefore, a uniaxial compressive strain, depicted by the arrows in FIG. 1C, is rendered on channel region 102 in strained PMOS-FET 130, which can enhance hole mobility in the device.
One drawback to this approach is that gate isolation spacers 108 are required to inhibit undesirable material growth on gate electrode 106 during epitaxial film growth to form strain-inducing source/drain regions 120, e.g. to inhibit the growth of silicon/germanium on a polysilicon gate electrode. The location of the strain-inducing source/drain regions 120 relative to channel region 102 is therefore restricted by the width of gate isolation spacers 108. Thus, the parasitic resistance-reducing ability and the strain-inducing ability of strain-inducing source/drain regions 120 may be limited. Tip extensions 110 may be formed in substrate 114 to reduce the resistance of strained PMOS-FET 130. However, tip extensions 110 are formed from the same material as channel region 102. Therefore, the lattice mismatch between tip extensions 110 and the channel region 102 is negligible, resulting in effectively no additional strain on the channel region 102 from tip extensions 110.
Thus, a semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described herein.